发明名称 CONTROL SYSTEM
摘要 PURPOSE:To prevent control operation from being delayed even when a signal from a signal source is checked plural times by allowing a processor to input the signal from the signal source by extending the duration of the signal through a pulse stretcher circuit. CONSTITUTION:The processor 1 supplies a control signal to an address setting circuit 8, decoder 6, and multiplexer MPX7. When the address in the signal coincides with the address set in the circuit 8, the circuit 8 outputs an H-level signal to the decoder 6, which is activated to drive a driving circuit 9 corresponding to the address, changing the switching mode of a latching relay 10. The MPX7 supplies a selected signal from the signal source 2 to the pulse stretcher circuit 23 only for the duration of the control signal. The circuit 23 extends the duration of the signal from the MPX7 and supplies the signal to the processor 1 through an input signal line 18, so the processor 1 makes a reception check several times within the duration of the signal.
申请公布号 JPS59109904(A) 申请公布日期 1984.06.25
申请号 JP19820220647 申请日期 1982.12.15
申请人 MATSUSHITA DENKO KK 发明人 MATSUBARA YUUSAKU
分类号 G05B19/05 主分类号 G05B19/05
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