| 摘要 |
<p>PURPOSE:To change a selecting signal for a selecting circuit on the basis of the change of a signal applied from the outside to an arithmetic circuit and an arithmetic selecting circuit by providing the arithmetic circuit and the arithmetic selecting circuit. CONSTITUTION:A delay signal 3' is used as a setting timing signal for a memory element group 7. When the timing signal is to be delayed for the set value, the number of steps of delay elements 2, 5 corresponding to the time to be delayed is specified by a binary code consisting of 2 bits. If the time is to be delayed by one step of the delay element, a binary code ''01'' is specified. Both the outputs of a register 9 and an external terminal 13 are inputted to an adder 10 to add both the values and the added result is applied to the 1st path 10'. When a selecting signal is applied to an external terminal 14 so that the arithmetic selecting circuit 12 selects the 1st path 10', a delay signal 4' is selected and supplied to the memory element group 7. When the setting of the timing signal is not changed, the contents of the register 9 is outputted to the selecting circuit as it is, so that the 3rd path 9' is selected.</p> |
