发明名称 ANALOG-DIGITAL CONVERTER
摘要 PURPOSE:To prevent the generation of deterimental defect of operation by providing a gate circuit between an encoder having split low-order bits and an encoder at the next stage so as to prevent outputs of plural subordinate encoders from being turned on at the same time. CONSTITUTION:An output of the 1st encoder having split low-order bits is connected to an input 1, an output of the 2nd encoder having split low-order bits is connected to an input 2, and respective outputs 1, 2 of logical circuits 8A', 8B' are inputted to a host encoder. Provided that active data is inputted to inputs 1, 2 at the same time, its control output 0 is applied to a gate circuit 9 from an NOR circuit 10A. Thus, a gate circuit 9 does not transfer the data of the input 2 to the output 2 and only the data of the input 1 is generaged at the output 1. Thus, a large error affecting plural encoders having low-order bits is not generated.
申请公布号 JPS59107629(A) 申请公布日期 1984.06.21
申请号 JP19820217221 申请日期 1982.12.10
申请人 MATSUSHITA DENKI SANGYO KK 发明人 MATSUZAWA AKIRA
分类号 H03M1/36;H03M1/12;H03M1/14 主分类号 H03M1/36
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