发明名称 SEMICONDUCTOR MEMORY CIRCUIT
摘要 PURPOSE:To control easily the potential of a digit line with the potential of a clamp circuit by generating both input signals to be supplied to a current switch circuit and the clamp circuit from the same 2nd current switch circuit. CONSTITUTION:With generation of a read-out input VINB, the output signal 21 of a decoder is compared with a reference potential 22 of the signal 21. When the signal is set at a low potential, the input VINB is set at a high potential, i.e., a selected potential. The base potential VYB of a clamp circuit is generated from the collector of a transistor having the reference voltage VBB applied to its base. Thus transistors TR6 and 7 are driven via a TR23 which functions as an emitter follower. In this circuit the breaking time of the signal VYB can be controlled by an emitter current source 24 of the TR23. Therefore the digit line potential can be easily decided by the potential VYB when the potentials of digit lines 13 and 14 are reduced down to a non-selection level from a selection level.
申请公布号 JPS59107486(A) 申请公布日期 1984.06.21
申请号 JP19820216822 申请日期 1982.12.13
申请人 HITACHI SEISAKUSHO KK 发明人 YAMAGUCHI KUNIHIKO;KANETANI KAZUO
分类号 G11C11/414;G11C11/34;(IPC1-7):11C11/34 主分类号 G11C11/414
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