发明名称 |
FET CONVOLVED LOGIC |
摘要 |
A generic FET logic circuit topology is disclosed which employs non-thresholded path routing to eliminate logic transition times in the critical data path. Non-threshold logic performs logic operations with non-inverting unity gain OR and AND functions. The propagation time through the logic matrix is therefore similar to the delay through a chain of linear amplifiers, as contrasted to an algebraic accumulation of delays with conventional logic techniques. This results in an N-factor improvement in the power-delay product over conventional techniques, where N is the number of logic operations being performed. |
申请公布号 |
DE3163633(D1) |
申请公布日期 |
1984.06.20 |
申请号 |
DE19813163633 |
申请日期 |
1981.07.14 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ROSENBLUTH, WILLIAM;WILLIAMS, THOMAS ALBERT |
分类号 |
H03K19/0944;H01L27/118;H03K17/693;H03K19/096;H03M7/00;(IPC1-7):H03K19/09;H03K17/69 |
主分类号 |
H03K19/0944 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|