DIGITAL TELEVISION VIDEO SIGNAL STORAGE SYSTEM

摘要

A storage system for 625/50 PAL colour television signals sampled at 3 times colour subcarrier frequency (eg in a frame synchronizer) has a memory unit (6) composed of 10 memory cards. A burst controlled oscillator (11) derives clock pulses (12) and subcarrier frequency pulses (25). Write address generator (13) includes separation circuits (26, 28, 30) for providing vertical and horizontal pulses which control a vertical address generator (34) and a memory card selecting counter (36). The same address code can be used for 24 different samples, so that a line of 783 samples requires 26 addresses. If a vertical/horizontal address system were to be employed then 625 lines of 26 addresses would be required or 10 pulse 5 = 15 address bits. By transforming the addresses from the vertical address generator this can be reduced to 14 bits (ie the storage halved). A multiplier (41) multiplies the vertical address by a factor of 26 to give start address data which is loaded into a write memory address counter (43) at the start of each line. This counter is incremented once for each cycle of the card selecting counter (36). The read circuitry is similar.