Latch circuit with differential cascode current switch logic.

摘要

The set/reset latch circuit comprises a multi-level differential cascode current switch (DCCS) tree (11) operable to develop set and reset control pulses in response to logic input signals, a constant current source (10) two load resistors (14-L, 14-R), a bistable device (12) comprising a cross-coupled pairs of transistors and switching from a first state to a second state in response to respectively to the set and reset control pulses. The DCCS tree (11) includes means (16) for connecting the current source (10) to the bistable device (12) selectively through one of two different serial current paths of the tree (11) to provide a current to one of the load resistors (14-L, 14-R) through one of the cross coupled pair of transistors to hold the bistable device in one state in the absence of the set and reset control pulses.