| 摘要 |
PURPOSE:To obtain a high integration density and high speed read only memory by arranging a plurality of polycrystalline silicon layer belts and a plurality of conductive layer belts which are orthogonally crossing through an insulating film, providing contacts to the intersecting points of them in accordance with stored data and simultaneously by forming the P-N junctions to the contact. CONSTITUTION:In the case of reading the bit B1 of memory array MA, a voltage is given only to the conductive layer 41 and the conductive layers 42, 43 are set to 0V or open. When only the switching transistor 81 is opened, an input of read inverter circuit IN becomes ''1'' and ''0'' is output as the output signal. In the case of reading the bit B2 of memory array MA, a voltage is applied only to the conductive layer 42 and simultaneously only the switching transistor 81 is turned ON. In this case, the silicon layer 11 becomes open since contact does not exist at the position of bit B2 but an input of the read inverter circuit IN becomes ''0'' due to the depression type transistor DT and ''1'' is output. As described above, content of memory array MA can be read. |
