| 摘要 |
PURPOSE:To realize a time division bidirectional transmitter and receiver with decreased circuit scale and delay time, by using a buffer register so that a signal is outputted in the same order as the input, and the input and output can be performed in independent timing. CONSTITUTION:Transmission information on a line 14 is inputted to a serial- parallel conversion circuit 25 at transmission side. A parallel output in M bits is inputted to a transmission buffer register 26 of M bits and N stages, and the N-th output is outputed from a parallel-serial conversion circuit 27, received information is inputted from a line 18 to a serial parallel conversion circuit 28 and transmitted to a line 22 via a buffer register 29 and a parallel-serial conversion circuit 31 the same as the transmission side. The shift to each stage in the registers 26 and 29 is controlled with an output of control circuits 32 and 33 receiving an output of a timing generating circuit 34, the timing at terminals 39 and 41 is made from a reception frame of the line 18, clock frequencies of each information on the lines 14 and 22 are coincident with each other and each timing signal at terminals 37 and 38 is made by using the timing of the line 18 as a reference. |
