| 摘要 |
PURPOSE:To eliminate substantially the level variance of an output terminal within the switching transient time of a switch of a synthesizing circuit, by setting the resistance value of a resistor connected in series to the switch at a level sufficiently larger than the impedance of an input terminal and sufficiently smaller than the impedance of an output terminal, respectively. CONSTITUTION:When the input level difference is approximately zero, switches 11 and 13 are turned on. An equivalent circuit of this case is shown in a diagram (a), where V1 and V2 show the output voltage of amplifiers 20 and 21, respectively, r1 is the input impedance of an amplifier 22, r2 is the output impedance of amplifiers 20 and 21 and Vout shows the voltage that is applied to the input of the amplifier 22. If r1>R>r2 is satisfied, Vout (v1+v2)/2 is obtained. Then the switch 11 is turned off when the input level of a receiver is greatly reduced and the S/N improvement quantity is negative. In this case, the output levels have coincidence like the case of the diagram (a). The transient level variance due to the characteristics of the switch 11 is not generated also within the transient time from the diagram (a) to (b). |
