| 摘要 |
A high-speed parallel adder, using MOS technology, for two numbers represented with n positions in the natural binary code consists of stages (m...j, i, 0) with similar internal circuit, the carry input (ej) of one stage (j) being connected to the carry output (di) of the next lower stage (i) and the carry input (eO) of the lowest value stage being at the circuit zero. The individual stages in each case contain a first complex gate (1j), at the output of which the sum signal (sj or si) is present and which contains two AND operations (11j, 12j) and one OR operation (14j), the outputs of the AND operations being present at the inputs of the NOR operation (13j); a second complex gate with a NOR operation (23j) and an AND operation (21j), the output of which is present at the first input of the NOR operation (23j) - the output of which is the carry output (dj) - and the first input of which is present at the carry input (ej); a NAND gate (6j) and a NOR gate (3j) each with two inputs for the two non-inverted or inverted position signals (aj, bj or ai, bi), which are passed alternately to the adjacent stages (j, i), the output of the NAND gate (6j) being connected via an inverter (4j) to the second input of the NOR operation (23j) and to the second input of the OR operation (14j) and that of the NOR gate (3j) being connected to the second input of the AND operation (21j). <IMAGE> |
