| 摘要 |
<p>PURPOSE:To prevent malfunction at write by providing a difference to each of data write start time to a memory cell so as to suppress the generation of an instant large current change at write. CONSTITUTION:Signal delay circuits 361-367 are connected in multistage and cascade, and signals PGM2-PGM8 delayed sequentially are obtained by giving a control signal PGM to the delay circuit 361, and the signal PGM and the PGM2-PGM8 are given respectively to write control circuits 351-358. Since the fall time is delayed sequentially in the signals PGM2-PGM8 to the falling of the signal PGM, a difference is given to each of the write start time in writing a data by the control circuits 351-358. Thus, a current never starts flowing from a high voltage Vp at the same time at plural bits, thereby avoiding an instantaneous larger change in the write current. As a result, the generation of noise on the Vp power supply or a VS line is prevented.</p> |
