发明名称 ARITHMETICAL LOGICAL OPERATION CIRCUIT
摘要 PURPOSE:To reduce the number of constituent transistors (TR) of a fast ALU using CMOSTRs and simplify the constitution, and to suppress the occupation area on a chip in case of IC implementation. CONSTITUTION:Both NMOSTRs 4-1 and 4-4 are both in the off state at the beginning of a sampling period T2, so there is no danger of erroneous discharging of charge accumulated on a carry/borrow signal line in the transition from a precharging period T1 to the sampling period T2. Further, the NMOSTRs 4-1 and 4-4 are permitted to change only from an off state to an on state, so they never turn off after the carry/borrow signal line 4-2 is discharged temporarily. Therefore, charge on the carry/borrow signal line 4-2 are held in safety or discharged in a short time, so secure and fast operation is realized.
申请公布号 JPS5999541(A) 申请公布日期 1984.06.08
申请号 JP19820208862 申请日期 1982.11.29
申请人 NIPPON DENKI KK 发明人 KATORI SHIGETATSU
分类号 G06F7/501;G06F7/00;G06F7/50;G06F7/503 主分类号 G06F7/501
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