发明名称 ARITHMETIC SYSTEM OF SEQUENCER
摘要 PURPOSE:To shorten an execution time by using a truth value table for discriminating on the combination inhibition condition of a sequence circuit. CONSTITUTION:Sequence control data are supplied from an input circuit 4 to address buses A0-An of a memory 3. The memory 3 is stored with such a truth value table that an output appears at a data bus Dm when states of address buses A0-An are on the combination inhibition condition. The memory 3 receives the states of the address buses as data input and generates the corresponding output. The data bus Dm is connected to the interruption input of a CPU5. When an output is generated on the data bus Dm, the CPU5 accepts an interruption and executes a predetermined program for displaying the generation of the inhibition condition immediately.
申请公布号 JPS5999506(A) 申请公布日期 1984.06.08
申请号 JP19820209516 申请日期 1982.11.30
申请人 MATSUSHITA DENKO KK 发明人 INAMORI MICHIHIRO
分类号 G06F7/00;G05B23/02;G06F11/32 主分类号 G06F7/00
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