| 摘要 |
PURPOSE:To attain integration and miniaturization of a titled circuit by constituting a signal processing circuit with an edge trigger FF, two sets of counters and FFs. CONSTITUTION:An edge trigger FF10 such as a D-shape FF and a J-K-shape FF is provided, which reads an output pulse signal of a level discriminating circuits 5 in response to a prescribed cycle of an oscillating circuit 1 and changes a pulse signal into a continuous signal. An output Q and an output Q' of the FF10 are inputted to counter 11, 12 as a reset input and a clock pulse of the circuit 1 is set as a clock input. The FF13 sets an output of the counter 11 as the set input and the output of the counter 12 as the reset input, respectively. Thus, the role of an integrating circuit is constituted by a digital circuit without using a capacitor. |
