| 摘要 |
<p>A data word being stored in a dynamic RAM (64) is applied also to a shift register (193) arranged to divide the data word by a polynominal, the remainder after the division operation forming an error correction code word which is stored in a static RAM (86) at the same address as the data word is stored in the dynamic RAM (64). When the data word is read from the dynamic RAM (64), the division operation is again performed to generate a new error correction code word which is compared by a processor (62) with the original error correction code word from the static RAM (86). In the event of mismatch the error correction code word from the static RAM (86) is applied to the shift register (193) followed by zero bits, the number of applied zero bits being counted. Upon detection of a one bit in the last shift register stage (1920) and all zero bits in the remaining shift register stages (192a-192n) the bit of the data word having a position corresponding to the counted number of applied zero bits is complemented to correct the error. </p> |
