MOS Static RAM layout with polysilicon resistors over FET gates

摘要

A semiconductor device having a semiconductor substrate, wherein first and second insulating gate FET transistor connected, respectively, in series with first and second polycrystalline silicon layers acting as loads of first and second inverters are formed. The first polycrystalline silicon layer is provided above a gate electrode of the second insulation gate FET transistor, and the second polycrystalline silicon layer is provided above a gate electrode of the first insulation gate FET transistor.