| 摘要 |
PURPOSE:To restore the titled circuit to the normal status automatically even if the error is generated due to disturbance noise when interleaving is formed or released by providing the titled circuit with a malfunction detecting means for detecting a time series error generated between a writing means and a reading- out means to/from a data memory. CONSTITUTION:The malfunction detecting circuit 7 generates a reset signal when the error of an address value to be specified is generated by disturbance or the like in a writing counter 5 and a reading-out address latch 6. At the generation of the error of the address value in the writing address counter 5 or the reading- out address latch 6, one level of the lower three bits is turned to ''1'' when the level of a testing pulse A or B is ''1'', so that one of NAND gates 20 is turned to ''0'' and the level of a reset pulse is turned to ''0''. The pulse actuates a system reset generating circuit and resets the counter 5 and the latch 6 to initialize the address value. The address value repeats respective operations to return the respective parts to normal relation. |
