| 摘要 |
PURPOSE:To simplify control and avoid a decrease of cash memory capacity that can be used by a CPU by providing an auxiliary address converting and storing device lower in speed and larger in capacity than an address converting and storing device and an address conversion arithmetic means that executes address conversion arithmetic according to specified procedure. CONSTITUTION:When a logical address is given, to read out a corresponding physical address by association, a set of data stored in the storage position of an address converting and storing device TLB3 determined by lower Dg digits of given logical address is read out, and the logical address data of this set and the part of Dl-Dg digits on the given logical address are compared and coincidence/dissidence of the two is judged. When coincidence is judged, a conversion success signal is generated, and as physical address data of a set of read out data is made to the desired physical address, this address is outputted to the outside. When dissidence is judged, a conversion failure signal is generated. Thus, the presence of a set corresponding to the given logical address can by judged by one reading, and a high-speed operation becomes possible. |
