发明名称 MEMORY CONTROLLING SYSTEM
摘要 PURPOSE:To reduce lowering of performance in the case of cash mistake by providing a function of transferring reading request of data and memory address in a cash memory and a main memory simultaneously in a data processing device. CONSTITUTION:When an arithmetic processing unit 1 requests taking out of instruction and operand, request for reading out data is given to a cash memory 2 and a main memory 3 simultaneously, and data address is transferred by an address line 12. The main memory 3 starts reading of data regardless of whether this request makes cash hit or not. On the other hand, the cash memory section 2 investigates whether requested data exist in the section or not. In the case of cash hit, data are read out from the cash memory section 2 and transferred to the arithmetic unit 1 through a data line 13. At the same time, instruction to stop reading operation is given to the main memory 3, and the main memory 3 stops reading operation of data thereafter.
申请公布号 JPS5996585(A) 申请公布日期 1984.06.04
申请号 JP19820206351 申请日期 1982.11.25
申请人 MITSUBISHI DENKI KK 发明人 MURATA YUTAKA
分类号 G06F12/08;G06F13/00 主分类号 G06F12/08
代理机构 代理人
主权项
地址