| 摘要 |
The transfers comprise basic operations running according to "validation-acknowledgement" cycles. According to the invention, in order to permit the units to work at their own speed, each unit Ui fixes, under its sole control, basic execution times T1 to Tp for each operation and basic chaining times between the operation T12 to T(p-1)p, the first operation being an address transfer operation. In addition a prevention function, in each unit, is associated with the address transfer operation preventing any account being taken of a new address transfer operation if the address decoding operation underway in the unit Ui is not terminated. <IMAGE>
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