| 摘要 |
PURPOSE:To allow a controller to analyze the cause of a fault originating from the timing of a signal easily by providing the controller with the function of displaying its input/output state and variation in internal state with time on a time chart. CONSTITUTION:A CPU29 sets a specified time in a timer 26, which generates clock signals at intervals of the set time to interrupt the CPU29. Simultaneously, the CPU29 inputs the state of a specified signal from an input/output part 21 and stores the input data in a specific area of a memory 27. When the memory is full of data, data are overwritten from the beginning of the specific area. When set conditions are satisfied, the CPU29 stops fetching data from the input/ output part 21 and displays a message showing that on a CRT28. Consequently, data before the stopping time of the data fetch is written. The data from the input/output part 21 which are stored in the memory 27 are displayed on the CRT28 invariably in time chart form when requested on a keyboard 25. |
