SYNCHRONIZED RECEIVING CIRCUIT

摘要

PURPOSE:To attain the synchronising processing of input signals different in period by inserting a separate clock signal corresponding to the input signals to a space where two system clock signals are deleted. CONSTITUTION:An input signal IN1 having larger period than a system clock CLK0 is inputted to a register section 11 and stored temporarily by a delay signal a0 of a clock CLK1 attended with the signal IN1. An FF1 is set by a leading signal c1 of the clock CLK1, reset by a delay signal (b) of the clock CLK0, an OR signal is obtained by an OR from delay signals c4, c5 of a delay section 3 inputting an output signal c3 of an FF2 storing an ouput signal c2 of the FF1 for one clock period at each trailing of the clock CLK0, and the output signal c3 of the FF2 and an AND signal c6 without two signals' share is obtained by the clock CLK0 at the AND. On the other hand, a signal IN10 of the register section 11 is transferred and stored in a register section 12 by inputting the delay signal a1 and outputted as a reproduced input signal IN11. The signal IN11 is processed synchronizingly by obtaining a logical sum from the signals a2, c6 at the OR and forming a modified clock CLK2.