| 摘要 |
PURPOSE:To prevent the generation of an abnormal pulse at switching, by allowing a clock signal to have no delay time for a signal which controls the conduction state of an output gate when the output clock signal is switched from the clock signal of one system to that of the other. CONSTITUTION:Clock switching circuits 3 and 4 select simultaneously one of a clock signal a1 outputted from a clock signal generating circuit 1 and a clock signal a2 outputted from a clock signal generating circuit 2 on a basis of designation of inputted switching signals b1 and b2 and supply the selected signal as output clock signals d1 and d2 into their own systems. In this case, since the signal a2 inputted to a gate 307 through a buffer 406 and a buffer 313 has no delay time for a signal g1 which controls the conduction state of the gate 307, an abnormal pulse is not generated at the time when the signal a2 is outputted as the output signal d1. Similarly, an abnormal pulse is not generated when the output clock signal d1 is switched to the signal a1. |
