发明名称 HARDWARE STACK MEMORY CIRCUIT
摘要 PURPOSE:To use plural stack memories without lowering the throughput of a microprocessor, by making stack memories independent of one another with respect to hardware and connecting them to the microprocessor through a bus. CONSTITUTION:When a microprocessor 1 transmits an output instruction to a hardware stack control part 2, the value held in an up/down counter 10 is counted up by +1 with a stack push designating signal. It is transmitted as an address signal 12 to an RAM14, and data on a data bus 17 is held in an input data register 11, and an input signal 13 is written in the RAM14. Next, when the processor 1 transmits an input instruction from the control part 2, an output signal 16 from the RAM14 at the settling time of the address signal 12 is outputted onto the bus 17 through an output data register 15. After the processor 1 receives this data, the value held in the counter 10 is counted down by -1 with a stack pop designating signal 6 from the control part 2. Thus, the pop operation is completed.
申请公布号 JPS5994148(A) 申请公布日期 1984.05.30
申请号 JP19820203888 申请日期 1982.11.19
申请人 NIPPON DENKI KK 发明人 YAMANE OSAMU
分类号 G06F9/34;G06F9/42;G06F12/00;G11C7/00 主分类号 G06F9/34
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