| 摘要 |
PURPOSE:To generate easily and accurately a clock signal for readout of a memory cell by providing a dummy decoder which has the circuit constitution as either one of row and column decoders and supplies the same address signal as the other decoder. CONSTITUTION:For a column decoder line, the waveform of a decoder line D1-1 is change to a non-selection state from a selection state as well as to a low level L from a high level H. At the same time, the waveform of a decoder line D1 is changed to a selection state from a non-selection state as well as to the level H from the level L. However the change of the signal level has a time delay of about several tens ns until the non-selected line D1-1 and the selected line D1 are set at the levels L and H respectively since each decoder line has a large amount of floating capacity. During this transient period, the levels of the line D1-1 and A1 are set at the low level respectively. The same effect is obtained on a dummy decoder line. |
