发明名称 LATCH-UP PREVENTING CIRCUIT IN CMOS LSI
摘要 PURPOSE:To prevent latch-up effectively, by providing a capacitor on the way of a power supply line connecting a power supply terminal and an internal circuit. CONSTITUTION:N type regions 13a and 13b are formed at a proper interval on the surface of a P type well region 12 formed on an N type semiconductor substrate 11. A gate insulating film 14 having about 500Angstrom thickness is formed on the substrate surface between these regions 13a and 13b. A gate electrode 15 is formed on the film 14. This electrode 15 is connected to a power supply line 3, and the P type well region 12 is connected to the earth point of the circuit. Thus, the gate capacity of an MOSFET is used as a capacitor 4 for preventing latch-up.
申请公布号 JPS5994119(A) 申请公布日期 1984.05.30
申请号 JP19820201961 申请日期 1982.11.19
申请人 HITACHI SEISAKUSHO KK 发明人 MIYAKE NORIO;AKAZAWA TAKASHI
分类号 H03K19/003;G05F1/56;H01L27/092 主分类号 H03K19/003
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