| 摘要 |
PURPOSE:To prevent a malfunction due to a switch of validity display bits by providing a clear end display means to a validity display bit showing the validity of an address conversion pair. CONSTITUTION:When a display flip-flop 10 is set at logic ''1'' under its operation, the signal opposite to the hitherto one is selected among those signals which address selection means 7 and 8, a validity display bit selection means 9 and clear end display selection means 13 and 14 are all paired. That is, the means 7 selects a clear address 24 and then delivers it as an address bit 25. The means 8 selects an address bit 21, and the means 9 selects a validity display bit 28 which is read out of a validity display buffer 5. While the clear is started for a so far used validity display buffer 6. In such a way, an address converting operation is carried out at a high speed. |
