| 摘要 |
<p>PURPOSE:To prevent the malfunction of a logic circuit, by forming a release signal which starts the operation of a counter being stopped synchronously with a counter in operation on a basis of the signal from the operating counter out of plural counters and a control signal. CONSTITUTION:An output signal is pulled out from an FF, which is completely symmetric to a counter 2b, in a counter 2a and is inputted to an AND circuit 4, and the output signal of the circuit 4 is sent to a gate circuit 5. Thereafter, when a part symmetrical to the counter 2b in the counter 2a is set to (1, 1...1), the output signal of the circuit 5 is changed to the high level, and this signal is supplied to the circuit 5. At this time, when a halt instruction is released, the circuit 5 releases the operation stop state of the counter 2b at the timing of the part symmetrical to the counter 2b in the counter 2a becomes (0, 0...0), on a basis of the instruction of the circuit 4. Then, the counter 2b starts the operation synchronously with the counter 2b, and thus the malfunction of an ROM and an RAM is prevented.</p> |
