INTEGRAL MEMORY CIRCUIT WITH A SINGLE PULSE TRAIN TIMING CONTROL

摘要

An integral memory circuit includes a matrix of storage elements (11), and time controlled addressing and output elements (12, 13, 14, 17, 31; DO to D17, 31). Each output element includes a latch (100) and an output line (100) driving an external driver (26). Each output serves a set of storage elements connected to a node (24) to which the output line and latch are connected in parallel. All the time controlled elements are controlled by a single pulse train which enables the latch to hold the output line state when all other time controlled elements are disabled or reset and disables the latch when the other elements are selectively enabled thus eliminating any latch induced output delay.