| 摘要 |
PURPOSE:To make an information transmission system high-speed and high- reliability, by providing an FIFO memory for transmission, buffer for reception, and an FIFO timing control part for transmission between a serial-parallel converting part and a data bus. CONSTITUTION:When a signal from a terminal TE of a serial-parallel converting part 14 and a transmission permission signal 35 from a host processing device 5 reach an FIFO control part 34 for transmission, data is transmitted from a terminal OE of an FIFO32 for transmission. When data is stored in the FIFO32, a signal 22 is sent from a terminal OR of the FIFO32 to a terminal W of the serial-parallel converting part 14 through the control part 34. Meanwhile, the received clock of a received data is extracted by a clock extracting part 25 and is sent to a terminal RD of the converting part 14 through a code converting part 26. The signal from a terminal RE of the converting part 14 is sent to a DMA control part 16, and data is written to a memory part from the control part through a data bus 23 and an address bus 31 of a buffer 33. By a loop test signal 37, the turning-back test is performed with its own transmission data. |
