发明名称 |
DATA PROCESSING SYSTEM HAVING A MEMORY SYSTEM WHICH UTILIZES A CACHE MEMORY AND UNIQUE PIPELINING TECHNIQUES FOR PROVIDING ACCESS THERETO |
摘要 |
<p>A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macroinstructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.</p> |
申请公布号 |
CA1168377(A) |
申请公布日期 |
1984.05.29 |
申请号 |
CA19810376127 |
申请日期 |
1981.04.24 |
申请人 |
DATA GENERAL CORPORATION |
发明人 |
ZIEGLER, MICHAEL L.;DRUKE, MICHAEL B. |
分类号 |
G05B19/05;G06F11/10;G06F12/06;G06F12/08;(IPC1-7):G11C9/00;G06F13/06 |
主分类号 |
G05B19/05 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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