发明名称 DUAL DEADMAN TIMER CIRCUIT
摘要 A dual deadman timer circuit functions to reset a dual mode microprocessor in the event of loss of program control. The microprocessor has high and low power requirements corresponding to its two operating modes, and the deadman timer circuit also adjusts the output power level of an associated two-level power supply to ensure that sufficient power is available for the full operation of the microprocessor during reset. The deadman timer functions during both microprocessor modes and includes two level-sensitive input sections to ensure that the microprocessor is reset under an error condition.
申请公布号 CA1168371(A) 申请公布日期 1984.05.29
申请号 CA19810384443 申请日期 1981.08.24
申请人 MOTOROLA, INC. 发明人 DAVIS, WALTER L.;JACOBSON, JAMES E., JR.
分类号 G06F1/00;G06F1/24;G06F1/32;G06F9/00;G06F11/00;G06F11/14;G06F11/30;H04Q7/14 主分类号 G06F1/00
代理机构 代理人
主权项
地址
您可能感兴趣的专利