| 摘要 |
PURPOSE:To share the considerable part of hardware and at the same time to facilitate easy conversion into an IC by giving the digital processing to the signal of each track in series. CONSTITUTION:The signal Sp applied to an input terminal 10 is given to an A/D converter 13 and then sampled by a clock phi1 to be converted into digital data S1-S9. These data are successively delivered to a point A to be delayed by a D type flip-flop 14 by an amount equivalent to a cycle of the clock phi1 and then delivered successively to a point B. The data on points A and B are applied to an arithmetic circuit 15, and an operation A/A-B.N/2 is carried out to obtain the space between a zero cross point and the sampling phase position. If the data S1-S9 have values 10, 8, -2, -8, 2, 10, 10, 9 and -3 respectively, the arithmetic results -32, 2, 11, 2, 10, infinity , -72 and 2 are obtained at a point C respectively. While the outputs of points A and B are applied to an MSB (sine bit) detecting circuit 16. Thus the MSB is detected for each data. |
