| 摘要 |
A large-scale integrated circuit chip includes a plurality of bistables connected to combinational logic. In a diagnostic mode, the bistables are operated as a serial shift register, allowing test data to be shifted through the chip between diagnostic input and output pins (LPIN,LPOUT). In a chip test mode, the serial shift register is split into a number of shift register portions, each of which is connected between a separate pair of input and output pins. This allows test data to be shifted through all the shift register portions in parallel so as to speed up testing of the chip. |
