| 摘要 |
PURPOSE:To obtain a shift register of small pattern area and quick signal transfer time by constituting a self latch circuit by connecting an N channel enhancement type MOS FET which is conducted and controlled by inversion signal of controlling signal between connection point of the MOS FET and signal input terminal. CONSTITUTION:The fifth MOS FETQ5 of enhancement type and P channel type conducted and controlled by a controlling signal phi is connected between the connection point of the first and second MOS FET Q1, Q2 and an output terminal A2 (input terminal of next stage). At the same time, the sixth MOS FET Q6 of enhancement type and N channel type conducted and controlled by an inversion signal phi is connected between the connection point of the third and fourth MOS FET Q3, Q4 and an output terminal A2 to constitute a self latch circuit. The self latch circuit is cascade connected to constitute a shift register having state holding function for each transfer gate. By this constitution, the circuit performs transfer and holding of signals efficiently. The number of elements is smaller (about 3/4) than conventional circuit. As configuration is relatively simple, the area can be made small. |
