发明名称 PARITY CHECK DEVICE
摘要 PURPOSE:To generate no parity error even if a CPU executes an access to an area to which a parity bit is not added, by writing in advance a dummy data to which the parity bit is added, in an internal memory. CONSTITUTION:In case when an electric power source is turned on and a switch 2 is on, the head address and the final address of a memory 4, which are set in a program are referred to. A dummy data ''0'' is written in all areas between these addresses. At the same time, a parity bit is added to each dummy data by a parity setting/checking circuit 5. This write processing is continued until it reaches the final address from the head address. Thereafter, a data of a cassette type magnetic tape CMT6 is transferred to the memory 4, is written and also the parity bit is added. In this way, the parity bit is added to all areas of the memory 4.
申请公布号 JPS5987556(A) 申请公布日期 1984.05.21
申请号 JP19820198095 申请日期 1982.11.10
申请人 TATEISHI DENKI KK 发明人 NOMOTO TAKASHI
分类号 G06F11/10 主分类号 G06F11/10
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