发明名称 PSEUDO ERROR GENERATING SYSTEM
摘要 PURPOSE:To inspect easily a retrying function in case when an intermittent fault and a fixed fault are generated, by providing a pseudo error generation frequency register and a subtraction counter, and controlling the generation frequency of a pseudo error. CONSTITUTION:A pseudo error generation frequency register PECOUNT11 is a register which can be written from an external device, and holds the generation frequency of a pseudo error. Bits 0-3 are connected to a subtraction counter 12, are updated by -1 each by an output signal from an AND gate 15, and the pseudo error is generated until all the bits become ''0''. A detecting circuit 13 turns on a signal GE1 when it is detected that the pseudo error generation frequency indicated by the register 11 exceeds ''1''. While the signal GE1 is on, AND gates 31-3n send pseudo error signals PE1-PEn to circuits 41-4n. Also, the signal GE1 is supplied to one terminal of the gate 15. A detecting circuit 14 detects that the pseudo error generation frequency indicated by the register 11 is ''1'', turns on a signal EQ1, and it is supplied to one terminal of an AND gate 16.
申请公布号 JPS5987560(A) 申请公布日期 1984.05.21
申请号 JP19820197801 申请日期 1982.11.12
申请人 FUJITSU KK 发明人 IKEDA YASUSHI
分类号 G06F11/22;G06F11/00;G06F11/14 主分类号 G06F11/22
代理机构 代理人
主权项
地址