发明名称 VERTICAL PNP TRANSISTOR
摘要 PURPOSE:To reduce the variation of the current amplification factor of a vertical PNP transistor according to the variation of the emitter area, and to enable to hold the current amplification factor at a high level even at a small current by a method wherein a current to flow in the neighborhood of the surface of emitter-base junction is intercepted. CONSTITUTION:After a vertical PNP transistor is formed, a high concentration N<+> type impurity region 18 is provided as to surround an emitter region 17 in a base region 15 on the side of junction between the emitter region 17 and the base region 15. When impurity concentration of the N<+> type impurity region 18 surrounding the emitter region 17 is 5X10<18>cm<-3> or more, a surface current can be made small as allowable to be ignored. Width of the N<+> type impurity region is made to the extent not to exceed the N<-> type impurity ion implanted region 15. Moreover although depth of the N<+> type impurity region 18 may be made deeper than the emitter region, but it is not desirable to perform diffusion excessively deep to result in the reduction of the withstand voltage between the N<+> type impurity region 18 and a collector region 13'.
申请公布号 JPS5987861(A) 申请公布日期 1984.05.21
申请号 JP19820197106 申请日期 1982.11.10
申请人 TOSHIBA KK 发明人 TAKAOKI KIYOSHI;KINOSHITA HIROSHI;TAKAHASHI KOUICHI
分类号 H01L29/73;H01L21/331;H01L29/72;(IPC1-7):01L29/72 主分类号 H01L29/73
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