| 摘要 |
PURPOSE:To reduce a control signal and to simplify a circuit by applying a synchronizing signal to a latch register from the outside, when plural logical blocks are arranged and time divided and processed. CONSTITUTION:A data inputted to a register A is divided into registers B1, B2, and delayed by 2tau in delay elements b1, b2, respectively, and is stored in a register C. Also, the contents of the register C is divided into registers D1-D4, are supplied to registers E1-E4 through delay elements d1-D4, respectively, and are stored in a register F. Latch registers B'-F' are synchronized by a start signal of a period 1tau, and control the corresponding registers B1, B2, C, D1-D4, E1-E4 and F, respectively. That is to say, the register C and the register F are controlled by 1-bit signal having two-patterns and a four-patterns 2-bit signal, respectively. |
