| 摘要 |
PURPOSE:To enable the separation and outputting of only single pulse train having a specified pulse interval into a filter output by a method wherein when a pulse train having a specified repetition interval is extracted, a corresponding gate number is given thereto to be memorized and read to output a pulse to a gate corresponding to the gate number each time a pulse of the pulse train is extracted. CONSTITUTION:Each time a pulse is inputted, an invalid gate number is written into an FIFO memory circuit 9 when the output of a logic circuit 5 is ''false'', and a gate number for selecting a specified filter output when it is ''true''. On the other hand, each time a pulse delayed by a specified time is inputted into a margin shift register 4 from the pulse output, a number of a gate is read from the FIFO memory circuit 9. The second gate designation circuit 11 is controlled by the output of the logic circuit 5 with respect to the pulse input coinciding with the pulse train already detected, namely, the pulse input when the output of the logic circuit 5 is ''true'' so that the same gate number continued to be written into the FIFO memory circuit 9. Only one system of the pulse trains having respective specified intervals is outputted to the filter output 6 of the gate. |
