发明名称 DIVISION PROCESSOR
摘要 PURPOSE:To shorten the time required for the division by feeding the upper value of the divided and the divisor of the data to be applied an arithmetic processor by switching to the addition or subtraction performed with a carrier of the arithmetic result of the preceding step, then applying clocks by an amount equivalent to the input bit width of the processor. CONSTITUTION:A shift register SHR having the bit width double as much as the input bit width at one side of an arithmetic processor ALU and a 1-bit left shift function is provided to the processor ALU which works on a microprogram. In addition, a carry register CR is provided to save the carry generated to the output together with a multiplexer MPX at the other divisor input side of the processor ALU. Then an MPU selects the data obtained by converting the divisor data into a positive data as an input of the other side of the processor ALU or the numerical value obtained by inverting said data with addition of +1 in accordance with the value of the CR. Then the value of the CR is set at the lowest bit when the SHR is shifted left by a bit. This operation is repeated.
申请公布号 JPS5985539(A) 申请公布日期 1984.05.17
申请号 JP19820195187 申请日期 1982.11.06
申请人 FUJITSU KK 发明人 SATOU NOBUYOSHI;SASOU HIDEYUKI;SAKURAI MITSUO
分类号 G06F7/537;G06F7/508;G06F7/52;G06F7/535 主分类号 G06F7/537
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