发明名称 |
A METHOD AND A DEVICE FOR TESTING A LOGIC CIRCUIT |
摘要 |
In a system for testing a logic circuit (1) which includes a plurality of flip-flops associated with a scanning path between scanning-in (SI) and scanning-out (SO) terminals thereof and a combination circuit including logic gates a parallel to series conversion is performed to reduce the time required to perform a test and to reduce the storage capacity of a memory (4) associated with the testing device. In the system, parallel input data is transformed to serial data by a shift register (51) and the serial data is then set into the flip-flops of the circuit (1). Serial output data from the circuit (1) is transformed into parallel data by the shift register (51) so that the data is output in parallel. |
申请公布号 |
DE3067437(D1) |
申请公布日期 |
1984.05.17 |
申请号 |
DE19803067437 |
申请日期 |
1980.07.24 |
申请人 |
FUJITSU LIMITED |
发明人 |
HATANO, YOSHINORI;WADA, KIYOSHI;MIDORIKAWA, ICHIRO |
分类号 |
G01R31/28;G01R31/317;G01R31/3185;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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