| 摘要 |
A microprocessor system has a central processing unit which includes an independent address data path 106 and an independent arithmetic logic unit (ALU) data path 104. Each. is capable of simultaneous operation during a clock cycle. The data paths have a shared input multiplexer 116 connected to receive information from an information bus 102. A shared bus register 120 is connected to receive the information from the input multiplexer, and the shared output multiplexer 158 is connected to receive information from the bus register and other units in the data paths to supply the information to the information bus. The ALU data path has a register file 166 incorporating at least one bi-directional shift register linked to another register in the register file. An internal counter 162 forms a portion of the ALU data path and supplies information both to the register file and to the ALU 110. The bus register is split into at least two one-byte registers to allow fast execution of byte instructions. A control unit 200 for the microprocessor system includes a programmable logic array (PLA) 206 having at least one routine for testing operation of the microprocessor system, together with a control line connected to a console of a system including the microprocessor system, to allow the user to initiate system tests from the console. Data and programs in the microprocessor system are protected against access or modification by an unauthorized user through an ABORT function. <IMAGE> |
