发明名称 INTEGRATED CIRCUIT
摘要 PURPOSE:To transmit the starting of a test without newly adding a terminal for the test by varying a mode when a detecting means detecting the variation of the cycle time of a clock tansmitted from the outside is provided and the variation is detected. CONSTITUTION:A test clock oscillation circuit 11 oscillates at some times such as quadruple as large as the CLOCKA8. When an up-counter 131 is operated at a CO cycle, 4 is transmitted over a storage circuit 141 on the completion of the cycle. An up-counter 132 is operated at a C1 cycle, and 4 is transmitted over a storage circuit 142 on the completion of the cycle. The up-counter 131 reaches 8 at a C3 cycle, an output from a subtraction circuit 15 reaches 4 when the value is transmitted over the storage circuit 141 on the completion of the C3 cycle, and a variation detecting circuit 16 detects the variation and its output reaches 1. The circuit 16 reaches 1 at a C4 cycle, and the circuit 16 reaches 0 at a C5 cycle. Consequently, the mode FF17 is inverted, and a test mode is brought. A pulse extending over 2 cycle is generated in an output from the variation detecting circuit 16 by extracting clocks by one or more on the completion of all tests. The mode FF17 is inverted again by the pulse and reaches 0, and a run mode is brought.
申请公布号 JPS5984537(A) 申请公布日期 1984.05.16
申请号 JP19820194647 申请日期 1982.11.08
申请人 TOSHIBA KK 发明人 KAMIYA SHIGEO;YAMAZAKI ISAMU;MIYATA MISAO;NISHIO SEIICHI
分类号 G01R31/26;F02B75/02;G01R31/28;G01R31/317;G01R31/3185;G06F11/22;H01L21/66;H01L21/82;H01L21/822;H01L27/04 主分类号 G01R31/26
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