发明名称 INTEGRATED CIRCUIT
摘要 PURPOSE:To execute a plurality of simultaneous tests for each block in the integrated circuit at high speed by regarding the content of an ROM memorizing a program as a mere data, arithmetically and logically operating the data by an ALU and investigating the result. CONSTITUTION:In a test executing addition to all words in a device such as an ROM 2, one word using the value of a program counter PC3 as an address is read from the ROM2, and set to an instruction register IR4. Addition is executed between the register and an accumulator register ACC5. The result of addition is set to the register ACC5 by the next clock. The operation is repeated to all words in the ROM2. When the test is executed to all words, the test is completed because the value of a counter register 11 reaches zero. The value of the register ACC5 must reach the sum of all words of the ROM2 at that time. Consequently, the value of the register ACC5 is investigated. The contents of all words of the ROM2 can be inspected by the test, and the function of the addition of the arithmetic logic operation unit ALU6 can also be inspected. Functions as registers of the instruction register IR4 and the register ACC5 can also be inspected from the result, and the function of the counting of the program counter PC3 can also be inspected.
申请公布号 JPS5984536(A) 申请公布日期 1984.05.16
申请号 JP19820194646 申请日期 1982.11.08
申请人 TOSHIBA KK 发明人 KAMIYA SHIGEO;YAMAZAKI ISAMU;MIYATA MISAO;NISHIO SEIICHI
分类号 G06F11/22;G06F11/273;G11C29/00;G11C29/02;H01L21/66;H01L21/82;H01L21/822;H01L27/04 主分类号 G06F11/22
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