| 摘要 |
PURPOSE:To prevent the occurrence of a lacing by providing an outputting circuit which inverts and outputs the output signal of an inverter circuit at a master/slave flip-flop circuit. CONSTITUTION:When the level change curve of the delayed share of a node N2 exceeds over the logic threshold voltage of an inverter circuit IV1, a node N3 changes from a low level to a high level. At such a case, since the conductatnce of all of the MOSFETs are set at the same values, DC transitions of the node N2 and a node N5 are of all the same. This is because that the high level is inputted to an input inverter circuit at a master side and a feedback inverter circuit IV5 at a slave side, and the low level to the feedback inverter circuit at the master side and the input inverter circuit IV3 at the slave side. Thereby, the occurrence of the lacing due to a monophasic clock signal can be prevented. |
