| 摘要 |
PURPOSE:To avoid a conflict between the count timing and reset timing, by sampling the rear edge of the final bit of a decoder to obtain a reset signal and resetting a dividing counter by said reset signal. CONSTITUTION:A time decoder is provided with a dividing counter 11, a decoder 12 and a reset circuit 20. The circuit 20 consists of an inverter 21 and D-FF22 and 23. The FF22 samples an input signal B6 at the rise of a timing signal S8. An AND circuit 24 rises at the rear edge of a signal S6 and delivers a reset signal S11 for the time equivalent to the pulse width of a clock pulse S1. |
