发明名称 PICTURE PROCESSING CIRCUIT
摘要 PURPOSE:To control dynamically the number of stages of a pipeline and make the delay time constant, by outputting the output from an arithmetic device, which processes an input video through a selecting circuit in a pipeline picture processing circuit. CONSTITUTION:A video signal 13 of a TV camera 1 is made binary by a binary circuit 2, and a video signal 14 is outputted. The signal 14 is inputted to a fundamental circuit 3, and a prescribed arithmetic result or the inputted video signal is selected by a selecting signal 9 to output signal 15. The signal 15 becomes an input signal of a fundamental circuit 4 of the next stage. Consequently, the number of stages is controlled practically with respect to an output 16 of the final stage. Normally, a reduced pattern has a delay time corresponding to the number of stages of fundamental circuits 3-5; and therefore, even if the number of stages of the pipeline is changed dynamically, the delay time of the output result of the final stage is always constant, and succeeding processings are facilitated.
申请公布号 JPS5983266(A) 申请公布日期 1984.05.14
申请号 JP19820193406 申请日期 1982.11.05
申请人 HITACHI SEISAKUSHO KK 发明人 MIYATAKE TAKAFUMI;UEDA HIROTADA;MATSUSHIMA HITOSHI;KASHIOKA SEIJI;EJIRI MASAKAZU
分类号 G06T1/20 主分类号 G06T1/20
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