| 摘要 |
PURPOSE:To generate exactly a clock signal after a decoding operation is completed, by inputting an output signal of a decoder line to an NOR circuit, and providing an internal clock generating circuit for using its output signal as a clock signal for reading out a memory cell. CONSTITUTION:The first internal clock generating circuit 10 inputs an address signal from an input buffer 1, and sends out an address determining clock signal phi1 to a line decoder 3 and a decoder 4, but does not generate a clock signal for deciding and latching an output level to an output latching circuit 5. The second internal clock generating circuit 11 inputs an output of the line decoder 3 and an output of the row decoder 4, sends out a clock signal phi3 for deciding and latching an output level for reading out a memory cell to the output latching circuit 5, is provided with an NOR gate 12, and makes an output of decoder lines D0-Dn of the row decoder 4 as its input. |
